VHDL INCLUDE STUFF
Libraries and Packages
A PACKAGE is VHDL's method of implementing libraries. Items can be declared in a package like CONSTANTS and FUNCTIONS. We have gone over CONSTANTS in a previous page, and will discuss FUNCTIONS in detail later. LIBRARIES are declared in VHDL using the LIBRARY KEYWORD:
library IEEE;
use IEEE.std_logic_1164.all; library METAMOR;
library SYNOPSYS;
library PN_PAK;
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The USE and the .all extenuation tells the compiler to use
all the elements/routine/functions contained in the IEEE.std_logic
library. This file is usually in text format and can be printed out and
viewed. It is VHDL code. In the FOUNDATION series
the file is located in :
active\vhdl\vhdl_lib\ieee.vhd
The same can be said for metamor.vhd and synopsys.vhd. It might be a good idea to stop and just take a look at these files.
Also in that directory is a new PACKAGE which we wrote ourselves called PN_PAK. The text of this package is shown below:
--------------------------------------------------------------------------
-- PACKAGE PN_pak -- -- Date: 16 Nov 96 -- Version: 1.0 Associated Professional Systems -- -- Description: PN sample routines. -- -- APS 1996 -- -------------------------------------------------------------------------- library ieee ;
PACKAGE PN_PAK IS
PACKAGE BODY PN_PAK IS
FUNCTION slvect2int(vect : std_logic_vector) RETURN INTEGER IS VARIABLE size : INTEGER RANGE vect'length-1 DOWNTO
0;
IF (vect(i) = '1') THEN
END LOOP;
-------------------------------------------------------------------------
FUNCTION int2slvect(int_value : INTEGER; size: INTEGER) RETURN std_logic_vector IS
IF ((int_value/(2**i)) REM 2) = 0 THEN
-------------------------------------------------------------------------
-- feedback bit variable
-- mask off all ones at tap positions
-- loop through all temp registers to calculate feedback
bit
--assign all but msbit since it has output bit
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PACKAGE PN_PAK IS declares the PACKAGE |
FUNCTION slvect2int(vect : std_logic_vector) RETURN INTEGER; |
--
-- Covert standard logic vector to integer -- FUNCTION slvect2int(vect : std_logic_vector) RETURN INTEGER IS VARIABLE size : INTEGER RANGE vect'length-1 DOWNTO
0;
IF (vect(i) = '1') THEN
END LOOP;
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library IEEE;
use IEEE.std_logic_1164.all; library METAMOR;
library SYNOPSYS;
library PN_PAK;
ENTITY X84DEMO IS PORT
attribute pinnum of DivCntIn : signal is "P10,P9,P8,P7,P6,P5,P4,P3";
SIGNAL Count: INTEGER RANGE 0 TO 255;
-- Divide input by Multiplier times the DivCntIn value
BEGIN DIVIDER: PROCESS
IF Count >= slvect2int(DivCntIn,8) THEN
END behave; |