VHDL DATA TYPES
There are many data types which can be used in VHDL. To keep to the concept of this Lab book we will restrict ourselves to the following types for our discussions:
Example:
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Example:
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Example:
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We also see an INTEGER we named Multiplier which is not a SIGNAL but is in fact a CONSTANT. This is exactly what it sounds like. The format for the CONSTANT is the same as the SIGNAL format except the := sign is used to assign the CONSTANT value. This value will be STATIC and can be assigned or manipulated throughout the code. In our example we use the value to set a CONSTANT Multiplier which sets is used for comparison in an IF THEN condition statement.
library IEEE;
use IEEE.std_logic_1164.all; library METAMOR;
library SYNOPSYS;
library PN_PAK;
ENTITY X84DEMO IS PORT
attribute pinnum of DivCntIn : signal is "P10,P9,P8,P7,P6,P5,P4,P3";
SIGNAL Count: INTEGER RANGE 0 TO 255;
-- Divide input by Multiplier times the DivCntIn value
BEGIN DIVIDER: PROCESS
IF Count >= slvect2int(DivCntIn,8) THEN
END behave; |