APS-X84 VHDL/FPGA SYNTHESIS TUTORIAL

LAB NUMBER 2
Selectable Logic Gates

The following VHDL code builds on to our AND GATE lab. In this LAB we will use some conditional statements to implement four logic functions:

library IEEE; 
 use IEEE.std_logic_1164.all; 

 library METAMOR; 
 use METAMOR.attributes.all; 

 library SYNOPSYS; 
 use SYNOPSYS.std_logic_arith.all; 
 use SYNOPSYS.std_logic_unsigned.all; 
 -- 
 -- Begin Entity (This is a comment) 
 -- 
 ENTITY SELGATE IS 
                PORT 
                  ( 
                          Ain:         in         STD_LOGIC; 
                          Bin:         in         STD_LOGIC ; 
                          SEL:      in       STD_LOGIC_VECTOR(1 downto 0); -- 2 bits 
                          COut:     out        STD_LOGIC 
                  ); 

             ATTRIBUTE pinnum of COut: signal is "P35"; 
             ATTRIBUTE pinnum of Ain: signal is "P3"; 
             ATTRIBUTE pinnum of Bin: signal is "P4"; 
             ATTRIBUTE pinnum of SEL: signal is "P6,P5"; 
 
 
 END SELGATE; 
 -- 
 -- Begin Architecture (This is a comment) 
 -- 
 ARCHITECTURE behave OF SELGATE IS 

 BEGIN 

                WITH  SEL select 
                     COut <= Ain AND Bin WHEN "00", 
                             Ain OR Bin WHEN  "01", 
                             Ain XOR Bin WHEN "10", 
                       NOT(Ain AND Bin)  WHEN others; 

 END behave; 

Click HERE if you wish to return to the AND GATE lab to refamiliarize yourself with the following processes:

1)  Open the X84Lab2 project in the Foundation Software projects.

2) Insure the project has been properly synthesized and routed.

3) Insure the X84Lab2.rbt file from the latest route version is stored in the X84Lab2C directory where the X84Lab2.exe file is located.

4) Execute the X84Lab2.exe program and you should see the following screen:

In this Lab we have used the WITH SEL concurrent, conditional statement to implement a programmable gate. Our C executable code is responsible for sending the control bits to the associated FPGA to select which two input gate behavior and what the two inputs will actually be. The X84 board''s utility LED should respond with the correct output (1=ON, 0=OFF).  The C++ code for this control code can be seen HERE.

Other gates behaviors like XOR are selectable as shown below.

Remember these LABs are intended to show the VHDL constructs and how it write then implement them. Other more complex examples will be presented after covering some of the basics. These Labs are covering an extremely large amount of information in that they do take the users all the way through actual implementation and control. This is not just simulation, but actual in circuit use!