APS-X84 VHDL/FPGA SYNTHESIS TUTORIAL

VHDL LANGUAGE ELEMENTS

OPERATORs

Every Language has operators whose function it is to operate on an object to manipulate and produce a changed object. We will divide the VHDL operators which we will focus on here into the following groups:

ASSIGNMENT OPERATORS  <=     :=
      <=    
          This is the most common. It assigns signals and ENTITY objects. This is not used for VARIABLES or CONSTANTS 

          SIGNAL Ain:   std_logic; 

          Ain <= '1';

 
      :=  
                  This operator is used to assign VARIABLES and CONSTANTS 
      VARIABLE MyValue :   INTEGER RANGE 7 DOWNTO 0; 
                   CONSTANT Multiplier : INTEGER RANGE 0 to 255 := 10; 
LOGICAL OPERATORS  AND OR NAND NOR XOR XNOR NOT
 
We won't go over the specifics here other than to say that these work as one would think, and operate on std_logic and std_logic_vectors and subtypes.
      SIGNAL Ain: std_logic; 
      SIGNAL Bin: std_logic; 
      SIGNAL COut: std_logic; 
      SIGNAL DOut: std_logic; 

      COut <= Ain AND Bin; --implements AND GATE 
      DOut <= Ain AND NOT Bin; -- implements And Gate with inverter on one input

      SIGNAL Ain: std_logic_vector(4 downto 0); 
      SIGNAL Bin: std_logic_vector(4 downto 0); 
      SIGNAL COut: std_logic_vector(4 downto 0); 

      COut <= Ain AND Bin; -- Ands all five bits of Ain with all five of Bin 
      DOut <= NOT Cout; -- Inverts all of Cout bits and assigns to Dout

RELATIONAL OPERATORS   =    /=    <    <=    >    >=
=         equal               if   A = '1'  then......
/=         not equal       if   A /= '1' then.... 
<          is less than    if  A < '1' then  
           more typical ly used on integers    if A_integer < 100  then....
<=       Less than or Equal to   if A_Integer <= 100 then....
>         Greater Than 
>=       Greater than or equal to
SHIFT Operators  sll  srl  sla  sra  rol  ror
SLL    shift left    --right most bits replace with zeros 
SRL    shift right -- left most bits replaced with zeros 
    "1001" sll 2        becomes 0100  
    "1001" srl 2       becomes 0010
SLA  shift left arithmetic  -- shifts left and fills the the new right most bits with the least significant bit of the original number 
SRA shift right arithmatic --shifts right and fills the the new left most bits with the most significant bit of the original number 
    "1001" sla 2       becomes 0111 
    "1001" sra 2        becomes 1110
ROL     Rotate Left   - rotates left and fills right most bits with bits shifted out from left side 
ROR    Rotate Right  - rotates right and fills left most bits with bits shifted out from rignt side 

"1001" rol 3      becomes 1100 
"1001" ror 3   becomes  0011 

ARITHMATIC OPERATORS *  /  mod  rem  +  -  **
*           MULTIPLIER                                 
    A_Integer <= B_Integer * 10; 
/           DIVIDE  
    A_Integer <= B_Integer / 10;
MOD   MODULOUS OPERATOR  
    A_Integer <= -7 MOD 4;  -- A_integer is 3  (mod keeps sign of second operator)
REM    REMAINDER OPERATOR  
    A_Integer <= -7 REM 4; -- A_Integer is -3  (rem  keeps sign of first operator)
+         Addition 
    A_Integer <= A_Integer + 1; -- increments A_Integer (hopefully inside a process)
-        Subtraction 
    A_Integer <= A_Integer - 1; -- decrements A_Integer (hopefully inside a process)
**     Exponential  
    A_Integer <= 2** B_Integer ; -- A_integer <= 2 to the B_Integer power
MISC OPERATORS   &(concatenation)    abs
&(concatenation) concatnates two vectors 
    SIGNAL A_Vect: std_logic_vector(8 downto 0); -- nine bits  

    A_Vect <= "000100"&"111";--

 
ABS (absolute operator)
CONDITIONAL STATEMENTS
WHEN  ELSE  CONCURRENT CONDITIONAL STATEMENT 
    My_Signal <= My_First_Value WHEN My_Vect="00" else 
                          My_Second_Value WHEN My_Vect="01" else 
                          My_Default_Value;  

    The signal My_Signal is assigned values based on conditions (in this case My_Vect's values). 

  
WITH SELECT CONCURRENT CONDITIONAL STATEMENT 
    WITH My_Vect select
      My_Signal <= My_First_Value WHEN "00",
                                    My_Second_Value WHEN "01", 
                                   My_Second_Value WHEN "01", 
                           My_Default_Value WHEN others; 

    Here we have the makings of a four to one mux. The reason we use WHEN others instead of "11" for the last condition is that we are going to be using the std_logic_vector DATA OBJECT which if you remember has more possibiliies than just 1 or 0. When using the WITH SELECT and the SEQUENTIAL equivalent CASE statement we must satisfy all conditions. This is the VHDL way. Compiler errors will result ifthis is not satisfied.

IF THEN ELSE  SEQUENTIAL CONDITIONAL STATEMENT 
    if then 

    if A='1' then  
       b<='0'; 
    end if; 

    if then else 

    if A = '1' then 
        B<='0'; 
    else 
         B<='1'; 
    end if;

This statement shows the basic form of the if then else construct. Since this is a sequential statement it must be used inside of a process. The statement above could have been more easily implemented by saying  B<=NOT A; But that is only true for this simple type example. 

           if then elsif 

    if Avect = "01" then 
        B <= '0'; 
    elsif AVect ="00" then 
        B <= C; 
    elsif AVect="10" then 
        B<=D; 
    else    --default condition 
       B <= B; 
    end if; 

    Notice how  the elsif is spelled.  

 
CASE STATEMENT SEQUENTIAL CONDITIONAL STATEMENT  
    case My_Signal is 
          when My_First_Value =>  
                 (do stuff here) 
          when My_Second_Value => 
                 (do other stuff here) 
          when others =>  
                 (do default stuff here) 
    end case; 
Example: 
    case bit_value is 
        when "000" => 
              answer <= '1'; 
        when "001" => 
               answer <=1; 
                A <= '0'; -- can do more than one statement 
               MyVect <= "110"; 
         when others => 
                answer <= answer; -default operation 
    end case;
Notice that the case operates on our signal bit_value, and the conditional when statements are terminated with a => operator which marks the begining og the conditional operation. Also notice the ens case staement which terminates the case statement.
LOOPS
FOR LOOP 
    for i in 7 downto 0 loop 
           if AVect (i)= '`1' then 
                 BVect(i)<= '0'; 
          end if ; 
    end loop;
The for loop is a sequential statement and can only be used inside of a PROCESS
WHILE LOOP 
    while (My_Val < 100) loop 
       My_Val <= My_Val +1; 
    end loop; 
The while loop is also a sequential statement and is used in PROCESSes