VHDL LANGUAGE ELEMENTS
OPERATORsEvery Language has operators whose function it is to operate on an object to manipulate and produce a changed object. We will divide the VHDL operators which we will focus on here into the following groups:
SIGNAL Ain: std_logic; Ain <= '1'; |
This operator is used to assign VARIABLES and CONSTANTS |
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CONSTANT Multiplier : INTEGER RANGE 0 to 255 := 10; |
SIGNAL Bin: std_logic; SIGNAL COut: std_logic; SIGNAL DOut: std_logic; COut <= Ain AND Bin; --implements AND
GATE
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SIGNAL Bin: std_logic_vector(4 downto 0); SIGNAL COut: std_logic_vector(4 downto 0); COut <= Ain AND Bin; -- Ands all five
bits of Ain with all five of Bin
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= equal if A = '1' then...... |
/= not equal if A /= '1' then.... |
<
is less than if A < '1' then
more typical ly used on integers if A_integer < 100 then.... |
<= Less than or Equal to if A_Integer <= 100 then.... |
> Greater Than |
>= Greater than or equal to |
SLL shift left
--right most bits replace with zeros
SRL shift right -- left most bits replaced with zeros
"1001" srl 2 becomes 0010 |
SLA shift left arithmetic -- shifts
left and fills the the new right most bits with the least significant bit
of the original number
SRA shift right arithmatic --shifts right and fills the the new left most bits with the most significant bit of the original number
"1001" sra 2 becomes 1110 |
ROL Rotate Left
- rotates left and fills right most bits with bits shifted out from left
side
ROR Rotate Right - rotates right and fills left most bits with bits shifted out from rignt side "1001" rol 3
becomes 1100
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*
MULTIPLIER
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/
DIVIDE
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MOD MODULOUS OPERATOR
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REM REMAINDER
OPERATOR
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+
Addition
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-
Subtraction
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** Exponential
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&(concatenation)
concatnates two vectors
A_Vect <= "000100"&"111";-- |
ABS (absolute operator) |
FOR LOOP
if AVect (i)= '`1' then BVect(i)<= '0'; end if ; end loop; |
WHILE LOOP
My_Val <= My_Val +1; end loop; |