This course introduces design principles of modern computer architecture.
Teaching Load (Spring 2017):
Office Hours: Saturday from 10:30AM to 12:00PM.
Teaching Assistant: Eng. Fatma Anwar
Course work and assesment (100 marks):
CAD Tools to be used are:
Active HDL Student Edition
https://www.aldec.com/en/products/fpga_simulation/active_hdl_student
Modelsim Student Edition
https://www.mentor.com/company/higher_ed/modelsim-student-edition
“Computer architecture: a quantitative approach.”, Patterson, David A., and John L. Hennessy. 5th ed
“Computer organization and design: the hardware/software interface”, Patterson, David A., and John L. Hennessy. 5th ed
“Digital Design and Computer Architecture”, David Harris, Sarah Harris, 2nd Edition
Lecture 1 | Introcuction | [PDF] |
Lecture 2 | Overview and Background | [PDF] |
Lecture 3 | Pipelining Review | [PDF] |
Lecture 4 | SystemVerilog | [PDF] |
Lecture 5 | Instruction Level Parallelism (ILP): Static Techniques | [PDF] |
Lecture 6 | ILP: Branch Prediction | [PDF] |
Lecture 7 | ILP:
Dynamic Scheduling Tomasulo Algorithm Examples |
[PDF],
[PDF] [1],[2],[3] |
Lecture 8 | ILP:
Speculative Execution Speculative Tomasulo Examples |
[PDF] [1],[2] |
Lecture 9 | ILP: Multiple Issue Processor | [PDF] |
Lecture 10 | ILP: Limits to ILP | [PDF] |
Lecture 11 | Thread Level Parallelsim | [PDF] |
Lecture 12 | Multiprocessor and Parallel Programs | [PDF] |
Lecture 13 | Shared Memory Multiprocessor and Cache Memory Review | [PDF] |
Lecture 14 | Cache Coherence |
[PDF] [PDF] |
Lecture 15 | Directory-Based Protocols | [PDF] |
Lecture 16 | Shared Memory Synchronization | [PDF] |
Sheet 1 | Modern Processor Design Principles | [PDF] |
Sheet 2 | Pipelined Processor Review |
[PDF] [PDF] |
Sheet 3 | Instruction-Level Parallelism | [PDF] |
Sheet 4 | Thread-Level Parallalism and Multicore processors | [PDF] |
Mid-term Exams | 2017 |
Final Exams | 2017 |